Need for Reset Synchronizer

Why do we need to synchronize the reset deassertion for asynchronous reset flops?

Given below is an asynchronous active low reset, positive clock edge trigerred D flip-flop. It consists of a master & slave latch in sequence. The master latch is enabled on low pulse of the input ‘CLK’ and the slave latch on the high pulse of the ‘CLK’. Thus data from ‘D’ get flopped to Q on the positive ‘CLK’ edge; when the master latch transfers the data to the slave latch.

On an asynchronous assertion of reset, both master and slave latches gets reset and the flop output is ‘0’.

What will happen when the reset gets deasserted asynchronously?

Assume RESET is deasserted just before the positive edge of the flop and D (D1) was stable ‘1’ throughout. The master latch won’t meet the setup time of the input, and at the positive edge of CLK when the master latches the data, the output Q1 can be in a metastable state. This metastable Q1 is transferred to Q(Q2) during the high pulse of ‘CLK’. Thus the flop output can become metastable if the RESET deassertion is not synchronized.

Figure below shows the reset synchronous scheme commonly used:

When RESET_in is asynchronously asserted both the flops get reset and the output ‘RESET_out’, which is fed to the flops, gets asynchronously asserted. On asynchronous deassertion of RESET_in, first flop may enter metastability, but the output of the second flop will be ‘0’. The first flop has 1 clock period to get out of metastability after which RESET_out will get de-asserted synchronously.

Timing Issues with Interrupt Detection Logic

The figure below shows a common architecture used in interrupt detection. How the pulse to the SET pin is generated won’t be discussed here. Assuming based on the interrupt configuration we will get an input pulse signal interrupt_in, what are the possible timing issues?

1. The first condition is interrupt_in should meet the minimum pulse width requirement for SET pin of the flop.
2. The other timing issue is when release of SET signal doesn’t meet the ‘recovery’ time of the flop. This will happen when SET is released close to the clock edge. Following are the different timing scenarios:

• When interrupt_clear = 0 and D is stable 1. In this case even if recovery time is not met, since Q & D are 1’b1, Q+1 = 1’b1 without any metastability issues.

• In this case interrupt_clear = 1 and hence D is stable 0. When SET is deasserted without meeting recovery time the flop can enter metastable condition as SET was trying to drive 1’b1 and D 1’b0, Q+1 can settle to 1 or 0. But the interrupt_out will get cleared in next clock cycle. If this is not an issue by design, you don’t have to worry about this timing issue.

NOTE: You will need a synchronizer at the output of this logic (since the interrupt_in may not be a synchronous signal). This synchronizer will take care of the metastable issue here as well

• In this case, SET is asserted for a short duration (which meets the minimum pulse width requirement) and deasserted near the clock edge. As shown in figure Q (interrupt_out) becomes 1 after a delay of Tset->Q. This value is fed back to the D of the flop after a delay of TQ->D (routing delay + combinational gate delay). Here the flop can enter metastability if Tsu doesn’t meet the setup time of the flop.

This timing requirement is not very evident and can get easily neglected. The result is you might miss interrupts in your design!! To avoid this timing issue the pulse with should be more than Tset->Q + TQ->D + Tsu.

Setup-time vs Hold-time

Here I would like to share some of my knowledge on setup & hold times. This is one of the basic concepts of digital design and a common question in technical interviews.

Setup-time is the minimum time before the active edge of the clock when data to be sampled should be stable and hold-time is the minimum time after the active edge of the clock when data sampled should remain stable.

This can be better explained with the figure where the clock and data is shown. The scenario discussed here is a common one with data travelling from FF1 to FF2 with a combinational circuit in between. The timing details are

T_clk = 10ns

T_setup = 3ns

T_hold = 2ns

The total delay for data to reach FF2 input from FF1 for Edge0 = 9ns, for Edge1 = 5ns and for Edge2 = 1ns. Clearly there is a setup violation at Edge1 for FF2 as data is expected to be stable by 7ns (10-3) and there is a hold violation at Edge2 since data was expected to be stable till 22ns (20+2).

How does the time period of clock effect setup and hold time?

By increasing the time-period we can get rid of the setup violation, but it doesn’t have any effect on hold violations. This can be explained in the above example as follows: If we increased the time period to 12ns, Edge1 will occur at 12ns where as first transition to FF2 will occur at 9ns (0+9). Thus the data is stable 3ns before the active edge of the clock. Now let’s check the case at Edge2; Edge2 will occur at 24ns where as data transition will occur at 25ns (24+1). Thus the hold violation remains the same.

The other ways of getting rid of setup violations are pipelining, clock skewing, more parallel processing etc. Hold violations can be rectified by adding buffers in the data path, clock skewing etc. Hold violations are always harder to rectify compared to setup violations.