Setup-time vs Hold-time

Here I would like to share some of my knowledge on setup & hold times. This is one of the basic concepts of digital design and a common question in technical interviews.

Setup-time is the minimum time before the active edge of the clock when data to be sampled should be stable and hold-time is the minimum time after the active edge of the clock when data sampled should remain stable.

This can be better explained with the figure where the clock and data is shown. The scenario discussed here is a common one with data travelling from FF1 to FF2 with a combinational circuit in between. The timing details are

T_clk = 10ns

T_setup = 3ns

T_hold = 2ns

The total delay for data to reach FF2 input from FF1 for Edge0 = 9ns, for Edge1 = 5ns and for Edge2 = 1ns. Clearly there is a setup violation at Edge1 for FF2 as data is expected to be stable by 7ns (10-3) and there is a hold violation at Edge2 since data was expected to be stable till 22ns (20+2).

How does the time period of clock effect setup and hold time?

By increasing the time-period we can get rid of the setup violation, but it doesn’t have any effect on hold violations. This can be explained in the above example as follows: If we increased the time period to 12ns, Edge1 will occur at 12ns where as first transition to FF2 will occur at 9ns (0+9). Thus the data is stable 3ns before the active edge of the clock. Now let’s check the case at Edge2; Edge2 will occur at 24ns where as data transition will occur at 25ns (24+1). Thus the hold violation remains the same.

The other ways of getting rid of setup violations are pipelining, clock skewing, more parallel processing etc. Hold violations can be rectified by adding buffers in the data path, clock skewing etc. Hold violations are always harder to rectify compared to setup violations.