Quiz: Clock and output gating

Consider the following scenario:

Inputs: clk, input, control

Outputs: output

Requirement: output is a flopped value of input when control is high. When control is low, output should be pulled to low irrespective of input. The flop should be clock-gated.

How to implement this logic?

1. Gate the input with control before it’s fed to the flop. The same control signal is used to gate the clock.

As shown in above diagram, when control signal goes low, the input to the flop is made 1’b0. Since control is also used to gate the clock, the new input never reaches the output. We need one more clk pulse to drive the output low.

2. Gate the output of the flop with control signal and clock is also gated by the control signal.

This scheme ensures the output becomes 1’b0 when control is made low and also clk to the flop is gated. But this is not a clean solution as we are adding a combinational logic to the output of the flop. This might have effect on timing.

3. Gate the input with control before it’s fed to the flop. Clock is gated by logic-or of control signal and output.

This scheme is similar to ‘1’ except that the control signal to clock-gater includes the output also. As long as control is high, clock is always fed to the flop. When control becomes low, clock will be present to the flop as long as output is high. This ensures that we get the extra pulse (3^rd pulse) we were missing in scheme ‘1’. The additional pulse makes output low which in turn ensures the clock to flop gets gated.

Efficient Usage of Clock-Gating

Here is a good EE Times article on clock-gating usage.

[PDF Version]

Clock Gating

WHY GATE THE CLOCK?
• Power Reduction: Battery powered systems require power consumption levels that can only be achieved through clock gating. State-of-the-industry products require clock gating to achieve competitive power consumption levels even in mains-powered systems.

• Logic Reduction: In some cases significant amounts of logic can be removed from a design by gating a clock. Most logic includes large numbers of registers that share the same enable signal. In these types of situations, each flop will require a mux to act as a data path enable. Generating a gated clock for these situations will allow removal or simplification of all these muxes.

WHY NOT GATE THE CLOCK?
• Transitional Hazards: Can cause spurious transitions on the clock signal thereby causing incorrect functionality.

• Timing Issues: Can be caused by new setup and hold requirements created by the clock gate.

• Design For Test: Issues can be caused by the inability of the test tool to control the clock of gated flops.

• Synchronous Reset: Can be a problem when the clock is gated.

• Clock Tree Generation: The inclusion of logic in the clock tree can cause problems building a balanced clock tree.

CLOCK GATE STANDARD CELL :
Figure below shows a possible clock gate Hard IP cell. The inclusion of a transparent latch allows almost a full clock (minus setup, hold, and skew) of propagation time.

Figure 1 – Latch Based Clock Gating Circuit

Figure 2 – Clock Gating Circuit with Optimal Scan Control Circuit

The ‘or’ gate forces the clock gate to enable GATED_CLK when either TEST_SE or EN are asserted. The inclusion of the TEST_SE input ensures that the flops in the clock gate domain can be scanned regardless of the state of EN. The TEST_SE and EN signals are synchronous with CLK and have setup and hold requirements relative to that clock. Constraints for the cell ensure these requirements are met. When CLK is low, the ‘and’ gate forces GATED_CLK low regardless of transitions on TEST_SE and EN. When CLK is low the latch is transparent allowing changes on TEST_SE and EN to propagate to the ‘Q’ output of the latch. When CLK goes high, the other input to the ‘and’ gate (‘Q’ out of the latch) has already settled due to the setup requirements, so the worse case rising edge propagation through the clock gate block is the propagation time through the ‘and’ gate. When CLK goes high, the latch holds the state of its ‘D’ input – changes on the TEST_SE and EN inputs do not affect GATED_CLK.

You can place the control point OR gate in front of or behind the latch. Latch-based clock gating requires that the enable signal always arrives after the trailing edge of the clock signal or the rising edge for a falling-edge clock signal. If the control point is inserted before the latch, it is impossible for the control point to violate this requirement. Inserting the control point after the latch causes performance degradation because a gate is added between the latch and the register. In addition, the TEST_SE signal must then transition after the trailing edge (rising edge for falling-edge signal) of the clock signal during test because it does not go through the latch; otherwise glitches in the resulting signal corrupt the clock signal.

It is also possible to insert a Flop in the gating signal path instead of a Latch as long as the update occurs at the flop output when the clock is in control at the gate. If a lock-up flop is used, it may be wise to combine the TEST_SE with the gating signal after the lock-up; otherwise the effect of a change to the TEST_SE doesn’t occur until after one or two edges of the clock have been applied.
Anyway without such test control logic (the OR gate), DFT rule checks would flag the gated clock as uncontrollable during scan, and prevent flip-flops from being converted to scan flops.

Clock tree synthesis must account for clock gating and ensure the clock gating signal will get to the gate before any state element is updated by that clock. This naturally happens if the clock tree ensures the clock signal edges appear at state element clock inputs at the same time (within some tolerance for skew), including state elements that gate this same clock.