False Path – Design Example

A false path is a physical path that is never functionally accessed by the design. An example for the same is shown below:

The highlighted path (FF2 -> Comb2 -> Mux1 -> Comb3 -> Mux2 -> FF3) can never be accessed by the design since SEL is shared by Mux1 & Mux2, and when SEL = 1, Mux2 chooses a different path. But the same path can be reported for timing violations by the synthesis/timing tools. So we have to enlighten these tools about the path by using ‘set_false_path’ command.

Multicycle Path – Design Example

A multicycle path is a flop-to-flop path where the logic delay in between the flops is permissible to take more than one clock cycle as per the design. An example for this is shown below:

As can be seen from figure, the multiplier (Path1 & Path2) can take two clock cycles to compute the output (ensured by the flopped enable signal) unlike the other logic paths – Q11->Combo1->D21, Q21->Combo1->D21, Q12->Combo3->D31 etc. The timing diagram for the same is also shown below for more clarity

The output Q32 changes in every two cycles. The synthesis/Timing tools have to be informed about this constraint using set_multicycle_path command. Else these tools will try to meet the timing through multiplier in one clock cycle, resulting in false timing violations, area increase etc

Need for Reset Synchronizer

Why do we need to synchronize the reset deassertion for asynchronous reset flops?

Given below is an asynchronous active low reset, positive clock edge trigerred D flip-flop. It consists of a master & slave latch in sequence. The master latch is enabled on low pulse of the input ‘CLK’ and the slave latch on the high pulse of the ‘CLK’. Thus data from ‘D’ get flopped to Q on the positive ‘CLK’ edge; when the master latch transfers the data to the slave latch.

On an asynchronous assertion of reset, both master and slave latches gets reset and the flop output is ‘0’.

What will happen when the reset gets deasserted asynchronously?

Assume RESET is deasserted just before the positive edge of the flop and D (D1) was stable ‘1’ throughout. The master latch won’t meet the setup time of the input, and at the positive edge of CLK when the master latches the data, the output Q1 can be in a metastable state. This metastable Q1 is transferred to Q(Q2) during the high pulse of ‘CLK’. Thus the flop output can become metastable if the RESET deassertion is not synchronized.

Figure below shows the reset synchronous scheme commonly used:

When RESET_in is asynchronously asserted both the flops get reset and the output ‘RESET_out’, which is fed to the flops, gets asynchronously asserted. On asynchronous deassertion of RESET_in, first flop may enter metastability, but the output of the second flop will be ‘0’. The first flop has 1 clock period to get out of metastability after which RESET_out will get de-asserted synchronously.