Quiz: Clock and output gating

Consider the following scenario:

Inputs: clk, input, control

Outputs: output

Requirement: output is a flopped value of input when control is high. When control is low, output should be pulled to low irrespective of input. The flop should be clock-gated.

How to implement this logic?

1. Gate the input with control before it’s fed to the flop. The same control signal is used to gate the clock.

As shown in above diagram, when control signal goes low, the input to the flop is made 1’b0. Since control is also used to gate the clock, the new input never reaches the output. We need one more clk pulse to drive the output low.

2. Gate the output of the flop with control signal and clock is also gated by the control signal.

This scheme ensures the output becomes 1’b0 when control is made low and also clk to the flop is gated. But this is not a clean solution as we are adding a combinational logic to the output of the flop. This might have effect on timing.

3. Gate the input with control before it’s fed to the flop. Clock is gated by logic-or of control signal and output.

This scheme is similar to ‘1’ except that the control signal to clock-gater includes the output also. As long as control is high, clock is always fed to the flop. When control becomes low, clock will be present to the flop as long as output is high. This ensures that we get the extra pulse (3^rd pulse) we were missing in scheme ‘1’. The additional pulse makes output low which in turn ensures the clock to flop gets gated.

Timing Issues with Interrupt Detection Logic

The figure below shows a common architecture used in interrupt detection. How the pulse to the SET pin is generated won’t be discussed here. Assuming based on the interrupt configuration we will get an input pulse signal interrupt_in, what are the possible timing issues?

1. The first condition is interrupt_in should meet the minimum pulse width requirement for SET pin of the flop.
2. The other timing issue is when release of SET signal doesn’t meet the ‘recovery’ time of the flop. This will happen when SET is released close to the clock edge. Following are the different timing scenarios:

• When interrupt_clear = 0 and D is stable 1. In this case even if recovery time is not met, since Q & D are 1’b1, Q+1 = 1’b1 without any metastability issues.

• In this case interrupt_clear = 1 and hence D is stable 0. When SET is deasserted without meeting recovery time the flop can enter metastable condition as SET was trying to drive 1’b1 and D 1’b0, Q+1 can settle to 1 or 0. But the interrupt_out will get cleared in next clock cycle. If this is not an issue by design, you don’t have to worry about this timing issue.

NOTE: You will need a synchronizer at the output of this logic (since the interrupt_in may not be a synchronous signal). This synchronizer will take care of the metastable issue here as well

• In this case, SET is asserted for a short duration (which meets the minimum pulse width requirement) and deasserted near the clock edge. As shown in figure Q (interrupt_out) becomes 1 after a delay of Tset->Q. This value is fed back to the D of the flop after a delay of TQ->D (routing delay + combinational gate delay). Here the flop can enter metastability if Tsu doesn’t meet the setup time of the flop.

This timing requirement is not very evident and can get easily neglected. The result is you might miss interrupts in your design!! To avoid this timing issue the pulse with should be more than Tset->Q + TQ->D + Tsu.

Efficient Usage of Clock-Gating

Here is a good EE Times article on clock-gating usage.

[PDF Version]