Design for Testability – Scan

The goal of DFT is to improve the probability of finding manufacturing defects caused by: dust particles, fab control problems etc while minimizing the cost of finding the defects. A chip will not work as per the specifications if there are any faults introduced in the production process. But the question is how to detect that. To run all the functional tests is very time consuming. The solution for this is called “Design for Testability” – where the design has additional circuit to check for potential faults. DFT aims at simplifying testing by modifying a design to improve the controllability, observability and predictability of internal signals of ASIC.

Controllability is defined as the ability to establish a specific signal logic value either low or high at each node in a circuit by setting values on the circuit’s inputs.

Observability is defined as the ability to determine the signal value at any node in a circuit by controlling the circuit’s inputs and observing its outputs.

Predictability is the ability to obtain known output values in response to given input stimuli.

DFT tools check for the structural correctness of the chip. Structural test makes no direct attempt to determine if the overall functionality of the circuit is correct. Instead, it tries to make sure that the circuit has been assembled correctly from some low-level building blocks as specified in a structural netlist, like looking for the presence of all specified logic gates, they are operating correctly, and connected properly. The stipulation is that if the netlist is correct (confirmed by netlist simulations), and structural testing has confirmed the correct assembly of the circuit elements, then the circuit should be functioning correctly.

One of the common DFT methods is Scan Testing using stuck-at fault test models. Scan design is a DFT technique involving specialized flip-flop or latch that allows data to be scanned in for control and to be scanned out for observation and can be activated in scan mode for test purposes. In this article we will concentrate on this topic.

But before that, what is Fault Model?

The basic assumptions regarding the nature of physical and logical faults in a combinational logic circuit is referred to as fault model. The most widely used fault model for digital logic circuits is that of a single node being permanently stuck at a logic value. This type of fault model is referred to as single stuck-at-fault model. The goal of test generation is to produce a complete fault detection test set (vector), that is, a set of tests that detect any detectable faults. By using stuck-at-fault model for combinatorial logic circuits and with algorithmic ATPG techniques, a high fault coverage test sets can be generated for testing ASIC.

The two essential parameters of an effective test with high fault coverage are controllability and observability – this means the inputs to all the nodes in a design should be controllable to any desired value and the outputs observable to detect the presence of any faults. But not all nodes are available as inputs/outputs to the chip – then how will we control/observe them? In Scan mode the flops in the design are used for this purpose by converting the normal flops to scan flops as shown below:

The two new inputs are SE – Scan enable and SI – Scan Input.

Using these scannable flops we should be able to drive any desired value at any node and observe the outputs at the pads by driving then through the scan chains (all scan flops acting as shift registers). The scan test design has two modes, a functional mode, which is the normal mode of operation, and a test mode, in which the flip-flops are accessed via the shift register configuration. A comprehensive test can be created by an Automatic Test Pattern Generation. The ATPG program targets a fault, configures the combinatorial logic to force the node to the opposite value and to allow that value to propagate to an “output”. The pattern is passed to the combinational inputs and the combination outputs are driven to the pads as follows:

Figure below shows a normal digital design which consists of ‘Combinational Logic’ being driven by a set of Flops and the outputs registered by another set of Flops.

Synchronous Logic Under Normal Mode of Operation

Step1: The input pattern is shifted to the stitched flops. During this mode scan_mode = 1

Test Mode of Operation

Step2: The chip is operated for 1 clock cycle in functional mode and the combinational output is ‘captured’ by the Flops.

Test Mode of Operation

Step3: The results are then shifted out to chip output pins and compared against the expected “good machine” results.

Test Mode of Operation

To summarize, the scan test operation on the tester is as follows: put the chip into test mode, load the scan chain, put the chip into functional mode, observe the primary outputs (to cover any logic between flip-flop and output buffer), set the primary inputs (to cover any logic between input buffer and flip-flop), execute one clock cycle, put the chip into test mode, observe the scan chain output, and start clocking the scan chain and observing the output to record the results from the flip-flops. The process then repeats, with the additional point that the first and last steps overlap one another; in other words, the new scan pattern is being loaded in to the scan chain while the results from the previous pattern are being shifted out.

One of the issues with this approach is the number of clock cycles required to load the scan chain. As designs get larger and larger, this time spent on the tester may become prohibitive. The first order solution is to use multiple scan chains loading in parallel. This works well if all scan chains are of approximately equal length. In a design with multiple clock domains, balancing scan chain length will likely require multiple clocks on the same scan chain.

As designs pass a million gates, even this technique of multiple scan chains might not be sufficient. You run out of tester time, I/O, or both. The way out is scan compression. This involves a very large number of short scan chains loaded through a decoder driven by a small number of inputs, and monitored through a small number of outputs, usually with some form of signature generation. The attributes you lose are the ability to arbitrarily load any value into any scan chain.

Debug using DFT structure:

In addition to being useful for manufacturing “go/no go” testing, scan chains can also be used to “debug” chip designs. In this context, the chip is exercised in normal “functional mode”. At any time, the chip clock can be stopped, and the chip re-configured into “test mode”. At this point the full internal state can be dumped out, or set to any desired values, by use of the scan chains. Another use of scan to aid debug consists of scanning in an initial state to all memory elements and then go back to functional mode to perform system debug. The advantage is to bring the system to a known state without going through many clock cycles.

Reference:

1. Design For Test by Dr. Paul D. Franzon

2. Tutorial on Design For Testability (DFT)  “An ASIC Design Philosophy for testability from Chips to Systems” – Keshava Iyengar Satish

3. http://www.vlsiip.com/pdf/dft.pdf

4. http://en.wikipedia.org/wiki/Design_For_Test

5.  http://billgascoyne.wordpress.com/2009/02/24/scan-test-basics/